Significant research and development efforts are currently directed towards designing and manufacturing nanoscale electronic devices, including nanoscale memories. Nanoscale electronics promise a number of advantages over microscale, photolithography-based electronics, including significantly reduced features sizes and the potential for self-assembly and for other relatively inexpensive, non-photolithography-based fabrication methods. However, the design and manufacture of nanoscale electronic devices present many new problems that need to be addressed prior to large-scale commercial production of nanoscale electronic devices and incorporation of nanoscale electronic devices into microscale and larger-scale systems, devices, and products.
Nanoscale crossbar-memory arrays are possible candidates for relatively near-term commercialization. Nanoscale crossbar-memory arrays can be composed of a first layer of approximately parallel nanowires overlain by a second layer of approximately parallel nanowires, the orientation of the nanowires of the first layer are approximately perpendicular to the nanowires of the second layer. A resistor is located at each point where a nanowire in the second layer overlaps a nanowire in the first layer and is called a “crossbar-memory junction.” The nanowires of the first layer are addressed through selective interconnections to microscale output signal lines of a first combined microscale/nanoscale encoder-demultiplexer, and the nanowires of the second layer are addressed through selective interconnections to microscale output signal lines of a second combined microscale/nanoscale encoder-demultiplexer. Resistors are located at selected combined microscale/nanoscale crossbar junctions of the encoder-demultiplexers. A nanowire address is input to an encoder via microscale address lines and is transformed into a pattern of addressed-nanowire selection voltages that are output by the encoder to the microscale output signal lines of the encoder-demultiplexer. Selection of the two nanowires that cross at a particular crossbar-memory junction by the two encoder-demultiplexers results in applying a defined voltage to the crossbar-memory junction selected by input of two nanowire addresses to the two encoder-demultiplexers.
Relatively large voltages can be applied to a given crossbar-memory junction to reversibly configure the resistor in a high-conductance state or low-conductance state, the particular conductance state obtained depending on the polarity of the applied voltage. However, application of voltages greater in magnitude than the voltages used to reversibly configure crossbar-memory junctions can irreversibly destroy the crossbar-memory junctions to which the greater voltages are applied. Each crossbar-memory junction serves as a single-bit memory element, storing a binary value “0” as a low conductance state and a binary value “1” as a high-conductance state.
Although the encoder-demultiplexers and the crossbar memories are similar in that both are implemented using nanoscale crossbars that have configurable resistors at the crossbar junctions, there are important differences between the resistors used in the two subsystems. The resistors in the memory array are used as memory storage elements, and are therefore electronically-reconfigurable. By contrast, the resistors in the encoder-demultiplexers are configured once at the time of manufacturing, and are stable thereafter. However, designers, manufacturers, and users of nanoscale crossbar-memory arrays have recognized a need for crossbar memory arrays with electronically-reconfigurable crossbar resistors at crossbar memory junctions that provide large voltage margins, defect tolerant properties, and can be used with encoder-demultiplexers that use redundant addressing schemes based on error-correcting codes. In addition, designers, manufacturers, and users have recognized a need for methods of writing information to and reading information stored in crossbar memory junctions.